Unverified Commit bf272145 authored by Birte Kristina Friesel's avatar Birte Kristina Friesel
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msp430fr5994lp: correctly document clock rates

parent b6206e83
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+2 −2
Original line number Diff line number Diff line
@@ -59,11 +59,11 @@ class Timer {
		inline void setup_hz(uint16_t const frequency) {
			TA0CTL = TASSEL__SMCLK | _TA0_MAIN_DIV;
			if (frequency < 32) {
				// 2 MHz base
				// 250 kHz base
				TA0EX0 = 7;
				TA0CCR0 = 250000UL / frequency;
			} else {
				// 250 kHz base
				// 2 MHz base
				TA0EX0 = 0;
				TA0CCR0 = 2000000UL / frequency;
			}